INTERLINE DYNAMIC VOLTAGE RESTORER PDF

Then a new device which is named Inter-line Dynamic Voltage Restorer (IDVR) is discussed. This device consists of two conventional DVRs which are installed. An interline dynamic voltage restorer (IDVR) is a novel c o m p e n s a t i o n piece of mitigation It is made of several dynamic voltage restorers (DVRs) with a. Index Terms—Dynamic voltage restorer, Interline dynamic voltage restorer, Current source inverter, SMES and Power quality.

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To successfully apply this concept, several constraints are addressed throughout the paper. In this case, the DF of the sourcing feeder will have a notable improvement with only a slight variation in DF of the receiving restorfr. In this paper an enhanced sag compensation scheme is proposed for capacitor supported DVR.

Interline dynamic voltage restorer (IDVR) Archives – ASOKA TECHNOLOGIES

DF improvement can be achieved via active and reactive power exchange PQ sharing between different feeders. Mathematical analysis is carried out for each individual component of the IDVR as modular models, which are then aggregated to generate the final model. To illustrate the effectiveness of the proposed method an analytical comparison is carried out with the existing phase jump compensation schemes.

The proposed technique has the advantage of votage the modelling of any flexible AC transmission system FACTS device in dynamic phasor mode when compared to other modelling techniques reported in the literature. It is clear from both the simulation and experimental results illustrated in this paper that the proposed zero-real volttage tracking technique applied to DVR-based compensation can result in superior performance compared to the traditional in-phase technique.

Electronics Nuclear engineering, Electrical restoeer Electronic Engineering. With the traditional in-phase technique, the compensation was performed and depended on the real power injected to the system. The proposed strategy improves the voltage quality of sensitive loads by protecting them against the grid voltage sags involving the phase jump.

The experimental results demonstrate the feasibility of the proposed phase jump compensation method for practical applications. In this paper, a new configuration has been proposed which not only improves the compensation capacity of the IDVR at high power factors, but also increases the performance of the compensator to dynamiv deep sags at fairly moderate power factors.

Computer planning and simulation of power systems require system components to be represented mathematically. The overall three-phase voltage signals during in-phase compensation simulation. The compensation was eventually forced to stop before the entire voltage sag period was finished.

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These advantages were achieved by decreasing the load power factor during sag condition. Winter Meetingvol. The experimental test results match those proposed using simulation, although some discrepancies due to the imperfect nature of the test circuit components were seen.

The ensure compatibility with transient stability programs, the analysis is performed for the fundamental frequency only, with other frequency components being truncated and without considering harmonics. Both the magnitude and phase displacement angle of the synthesized DVR voltage are precisely adjusted to achieve lower power utilization.

During sag period, active power can be transferred from a feeder to another one and voltage sags with long durations can be mitigated. A method for building a dynamic phasor model of an Interline Dynamic Voltage Restorer IDVR is presented, and the resulting model is tested in a simple radial distribution system. The real and reactive powers are calculated in real time in the tracking loop to achieve better conditions. Investigating the IDVR performance when the proposed method is applied for a sag with depth of 0.

Single line diagram of an IPFC in transmission system. Voltagr operational constraints have been identified and considered. This paper presents a utilization technique for enhancing the capabilities of dynamic voltage restorers DVRs. Then, more of the energy stored in the DC-link capacitor was utilized quickly, reaching its limitation within a shorter period.

An IDVR merely consists of several dynamic voltage restorers DVRs sharing a common dc link connecting independent feeders to secure electric power to critical loads. Abojlala, Khaled Issa and Holliday, Derrick and Xu, Lie Transient analysis of interline dynamic voltage restorer using dynamic phasor representation. The overall three-phase voltage signals during zero-real power tracking compensation simulation. This paper deals with improving the voltage quality of sensitive loads from voltage sags using dynamic voltage restorer DVR.

When the compensation was conducted using the proposed technique, less energy was used for the converter basic switching process. This enhancement can also be seen as a considerable reduction in dc link capacitor size for new installation. The main conclusions of this work can be summarized as follows: Further extension in compensation time can be achieved for intermediate sag depths. The restoger active power requirement associated with voltage phase jump compensation has caused a substantial rise in size and cost of dc link energy storage system of DVR.

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It also increases compensation time by operating in minimum active power mode through a controlled transition once the phase jump is compensated.

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The proposed concept has been supported with vpltage and experimental results. IDVR compensation capacity, however, depends greatly on the load power factor and a higher load power factor causes lower performance of IDVR.

Transient analysis of interline dynamic voltage restorer using dynamic phasor representation

An interline dynamic voltage restorer IDVR is a new device for sag mitigation which is made of several dynamic voltage restorers DVRs with a common DC link, where each DVR is connected in series voltabe a distribution feeder.

The DF of the sourcing feeder increases while the DF of the receiving feeder decreases. With this technique, none or less of the real power will be transferred to the system, which provides more for the DVR to cover a wider range of voltage sags, adding more flexible adaptive control to the solution of sag voltage disturbances.

In this paper, an enhanced sag compensation strategy is proposed that mitigates the phase jump in the load voltage while improving the overall sag compensation time.

While one of the DVRs compensates for the local voltage sag in its feeder, the other DVRs replenish the common dc-link voltage. The existing control strategies either mitigate the phase jump or improve the utilization of dc link energy by i reducing the amplitude of injected voltage, or ii optimizing the dc bus energy support.

Per-phase simulation gestorer for voltage sag condition at: Simulation and experimental results elucidate and substantiate the proposed concept. Then, experimental results on a scaled-down IDVR are presented to confirm the theoretical and simulation results. This technique results in less energy being taken out of the DC-link capacitor, resulting in smaller size requirements. Per-phase experimental and corresponding simulation results for DF improvement case: In this mode, theDFof one of the feeders is improved via active and reactive power exchange PQ sharing between feeders through the common dc link.

In this technique, the source voltages are sensed continuously and when the voltage sag is detected, the shunt reactances are switched into the circuit and decrease the load power factors to improve IDVR performance.